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	<title>CiteULike: dcastros Davidson</title>
	<description>CiteULike: dcastros Davidson</description>


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<item rdf:about="http://www.citeulike.org/user/dcastro/article/2782048">
    <title>Mean Time to Lose Lock for a PLL with Loop Delay under Thermal and Phase Noise Conditions</title>
    <link>http://www.citeulike.org/user/dcastro/article/2782048</link>
    <description>&lt;i&gt;Communications, 2007. ICC '07. IEEE International Conference on (2007), pp. 2888-2893.&lt;/i&gt;&lt;br /&gt;&lt;br /&gt;The growing demand for reliable communications leads to the need for very large mean time to lose lock (MTLL) of PLL based synchronization subsystems. These large MTLLs, of the order of months, cannot be simulated or tested in a lab. In this work a systematic approach is given to computing the MTLL of a second order PLL with parasitic delay at low SNR and high phase noise. Computed and simulated results are shown to be in good agreement for values that can be simulated.</description>
    <dc:title>Mean Time to Lose Lock for a PLL with Loop Delay under Thermal and Phase Noise Conditions</dc:title>

    <dc:creator>U Yehuday</dc:creator>
    <dc:creator>BZ Bobrovsky</dc:creator>
    <dc:creator>J Davidson</dc:creator>
    <dc:identifier>doi:10.1109/ICC.2007.480</dc:identifier>
    <dc:source>Communications, 2007. ICC '07. IEEE International Conference on (2007), pp. 2888-2893.</dc:source>
    <dc:date>2008-05-09T23:56:03-00:00</dc:date>
    <prism:publicationName>Communications, 2007. ICC '07. IEEE International Conference on</prism:publicationName>
    <prism:startingPage>2888</prism:startingPage>
    <prism:endingPage>2893</prism:endingPage>
    <prism:category>delay</prism:category>
    <prism:category>noise</prism:category>
    <prism:category>phase</prism:category>
    <prism:category>pll</prism:category>
    <prism:category>time</prism:category>
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<item rdf:about="http://www.citeulike.org/user/dcastro/article/2774764">
    <title>An overview of the modelling of an active microstrip patch array</title>
    <link>http://www.citeulike.org/user/dcastro/article/2774764</link>
    <description>&lt;i&gt;Communications and Signal Processing, 1998. COMSIG '98. Proceedings of the 1998 South African Symposium on (1998), pp. 373-378.&lt;/i&gt;&lt;br /&gt;&lt;br /&gt;This paper presents an overview of the use of the HP-EESof Communications Design Suite software and the finite-difference time-domain (FDTD) method for the analysis of an active microstrip patch array. The use of frequency- and time-domain simulation algorithms for the prediction of free-running and injection-locked oscillators is discussed. The modelling of the passive radiating part of the antenna using the FDTD method is covered. Free-running oscillators are shown to be handled accurately and efficiently using the harmonic-balance algorithm, but injection-locked oscillators are a source of difficulty. The FDTD method, when compared to measurements, gives good results for the input impedance and mutual coupling of the passive array</description>
    <dc:title>An overview of the modelling of an active microstrip patch array</dc:title>

    <dc:creator>K Williams</dc:creator>
    <dc:creator>HC Reader</dc:creator>
    <dc:creator>DB Davidson</dc:creator>
    <dc:identifier>doi:10.1109/COMSIG.1998.736985</dc:identifier>
    <dc:source>Communications and Signal Processing, 1998. COMSIG '98. Proceedings of the 1998 South African Symposium on (1998), pp. 373-378.</dc:source>
    <dc:date>2008-05-09T08:35:37-00:00</dc:date>
    <prism:publicationName>Communications and Signal Processing, 1998. COMSIG '98. Proceedings of the 1998 South African Symposium on</prism:publicationName>
    <prism:startingPage>373</prism:startingPage>
    <prism:endingPage>378</prism:endingPage>
    <prism:category>active</prism:category>
    <prism:category>antenna</prism:category>
    <prism:category>array</prism:category>
    <prism:category>model</prism:category>
    <prism:category>patch</prism:category>
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