Fri, 08 Aug 2008 20:13:03 BST CiteULike: dcastros Yehuday http://www.citeulike.org/user/dcastro/author/Yehuday CiteULike.org en-gb Copyright © 2004-2008 citeulike.org http://www.citeulike.org/user/dcastro/article/2782048 <i>Communications, 2007. ICC '07. IEEE International Conference on (2007), pp. 2888-2893.</i><br /><br />The growing demand for reliable communications leads to the need for very large mean time to lose lock (MTLL) of PLL based synchronization subsystems. These large MTLLs, of the order of months, cannot be simulated or tested in a lab. In this work a systematic approach is given to computing the MTLL of a second order PLL with parasitic delay at low SNR and high phase noise. Computed and simulated results are shown to be in good agreement for values that can be simulated. Mean Time to Lose Lock for a PLL with Loop Delay under Thermal and Phase Noise Conditions U Yehuday BZ Bobrovsky J Davidson doi:10.1109/ICC.2007.480 Communications, 2007. ICC '07. IEEE International Conference on (2007), pp. 2888-2893. 2008-05-09T23:56:03-00:00 2007 Communications, 2007. ICC '07. IEEE International Conference on 2888 2893 delay noise phase pll time