CiteULike: dcastros dll

Decision-directed coherent delay-lock tracking loop for DS-spread-spectrum signals

R de Gaudenzi — 2008-07-23T23:54:14-00:00

Communications, IEEE Transactions on, Vol. 39, No. 5. (1991), pp. 758-765.

The authors present a nonconventional joint data demodulation-pseudo-noise (PN) code tracking scheme for direct sequence (DS) spread-spectrum (SS) signals which solves problems of component imbalance and sensitivity with hardware simplicity and no performance degradation. An integrate-and-dump Costas loop is used for carrier recovery and data demodulation of the SS signal. Both data and carrier are then used to derive the baseband error signal of the code tracking loop. Moreover, a single passband correlator is used to perform the early-late correlation, leading to a hardware complexity equivalent to that of the tau-dither scheme, but without its loss in performance. Results of a thorough theoretical analysis of the system in an additive Gaussian noise (AWGN) environment are reported. They provide performance curves in terms of steady-state jitter and mean time to first lock loss. A superior jitter performance for low values of <e1>E</e1><sub>b</sub>/ <e1>N</e1><sub>0</sub> with respect to a traditional noncoherent delay lock loop (DLL) is shown, along with the potential gain of Manchester coding upon the more usual NRZ format

The Multipath Estimating Delay Lock Loop

RDJ van Nee — 2008-07-23T22:23:17-00:00

Spread Spectrum Techniques and Applications, 1992. ISSTA 92. IEEE Second International Symposium on (1992), pp. 39-42.

Extended tracking range delay-locked loop

A Wilde — 2008-06-02T07:14:33-00:00

Communications, 1995. ICC '95 Seattle, 'Gateway to Globalization', 1995 IEEE International Conference on, Vol. 2 (1995), pp. 1051-1054 vol.2.

In spread spectrum systems PN-code tracking is a crucial performance aspect. The delay-locked loop (DLL) is an appropriate device to guarantee fine synchronization. In this paper, a modified extended tracking range DLL is proposed. In the design of a DLL there is a tradeoff between tracking jitter and tracking range. The loop noise in an extended tracking range DLL is normally increased since more correlators are used. The jitter performance is improved by selecting the two strongest extended DLL branches. This modifies the extended DLL detector S-curve only slightly while reducing the noise power in the loop considerably

A semidigital dual delay-locked loop

S Sidiropoulos — 2008-06-02T06:48:42-00:00

Solid-State Circuits, IEEE Journal of, Vol. 32, No. 11. (1997), pp. 1683-1692.

This paper describes a dual delay-locked loop architecture which achieves low jitter, unlimited (modulo 2π) phase shift, and large operating range. The architecture employs a core loop to generate coarsely spaced clocks, which are then used by a peripheral loop to generate the main system clock through phase interpolation. The design of an experimental prototype in a 0.8-μm CMOS technology is described. The prototype achieves an operating range of 80 kHz-400 MHz. At 250 MHz, its peak-to-peak jitter with quiescent supply is 68 ps, and its jitter supply sensitivity is 0.4 ps/mV

An Approach to the Analysis of Performance of Quasi-Optimum Digital Phase-Locked Loops

D Polk — 2008-05-22T09:26:46-00:00

Communications, IEEE Transactions on [legacy, pre - 1988], Vol. 21, No. 6. (1973), pp. 733-738.

An approach to the analysis of performance of quasioptimum digital phase-locked loops (DPLL's) is presented. An expression for the characteristic function of the prior error in the state estimate is derived, and from this expression an infinite dimensional equation for the prior error variance is obtained. The prior errorvariance equation is a function of the communication system model and the DPLL gain and is independent of the method used to derive the DPLL gain. Two approximations are discussed for reducing the prior error-variance equation to finite dimension. The effectiveness of one approximation in analyzing DPLL performance is studied.

A Comprehensive Phase-Transfer Model for Delay-Locked Loops

JR Burnham — 2008-05-22T09:25:57-00:00

Custom Integrated Circuits Conference, 2007. CICC '07. IEEE (2007), pp. 627-630.

This paper presents a comprehensive model for analyzing the behavior of an analog delay-locked loop (DLL). Unlike previous models, the proposed version includes both constant and variable phase-offset terms, making it possible to calculate jitter transfer characteristics, stability, and static phase errors from a single unified model. The topology more closely approximates the underlying architecture of the DLL, resulting in improved accuracy and enabling better tradeoffs between bandwidth, stability, and power.

The Generalized Delay-Locked Loop

A Wilde — 2008-05-22T09:10:51-00:00

Wireless Personal Communications, Vol. 8, No. 2. (1998), pp. 113-130.

The delay-locked loop (DLL) is a synchronization device that is widely used for PN-code tracking in spread spectrum systems. The error detector characteristic (S-curve) of the DLL has a major impact on the performance. Using more than two correlators will extend the tracking range of the S-curve. The Generalized DLL (GenDLL) theory provides a concept to analyze a large class of DLL configurations including the classical DLL. The focus of the performance criteria is on tracking jitter and the mean time to lose lock (MTLL). It is shown that the MTLL can be considerably improved by using extended S-curves. However, the tracking jitter is increased by additional correlators. The tradeoff between the two criteria is explained. With the GenDLL theory loop configurations can be designed having both low tracking jitter and high loop robustness against loss of lock.

Acquisition Behavior of a First-Order Digital Phase-Locked Loop

W Lindsey — 2008-05-22T09:06:39-00:00

Communications, IEEE Transactions on [legacy, pre - 1988], Vol. 26, No. 9. (1978), pp. 1364-1370.

A general "phase-plane" technique for investigating the stability of nonlinear difference equation is described and applied to determine the stability criterion of a first-order digital phase-locked loop (DPLL). If the loop is stable, it is shown that acquisition behavior can be modeled as a first passage time problem. Using this model, one can evaluate the acquisition probability and the mean time to acquire, from the appropriate Chapman-Kolmogorov (C-K) equation describing the transition of the phase error sequence. This approach is verified by direct simulation.

PLL/DLL system noise analysis for low jitter clock synthesizer design

Beomsup Kim — 2008-05-22T09:05:58-00:00

Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on, Vol. 4 (1994), pp. 31-34 vol.4.

This paper presents an analytical model for timing jitter accumulation in ring-oscillator based phase-locked-loops (PLL). The timing jitter of the system is shown to depend on the jitter in the ring-oscillator and an accumulation factor which is inversely proportional to the bandwidth of the phase-locked-loop. Further analysis shows that for delay-locked-loops (DLL), which use an inverter delay chain that is not configured as a ring-oscillator, there is no noise enhancement since noise jitter events do not contribute to the starting point of the next clock cycle. Finally, theoretical predictions for overall jitter are compared to behavioral simulations with good agreement

The performance of the all-digital data transition tracking loop using nonlinear analysis

A Mileant — 2008-05-22T08:58:49-00:00

Communications, IEEE Transactions on, Vol. 43, No. 234. (1995), pp. 1202-1215.

This paper describes the performance of the all digital data transition tracking loop (DTTL) with coherent and noncoherent sampling using nonlinear theory. The effects of few samples per symbol and of non-commensurate sampling and symbol rates are addressed and analyzed for perfectly square pulses as well as filtered pulses. Their impact on the probability density and variance of the phase error are quantified through computer simulations. It is shown that the performance of the all-digital DTTL approaches its analog counterpart when the sampling and symbol rates are noncommensurate (i.e., the number of samples per symbol is irrational). The phase error variance for an even number of samples per symbol is also shown to degrade compared to an odd number of samples per symbol

Performance analysis of digital delay lock loops in the presence of Doppler shift

Nan-Yang Yen — 2008-05-21T12:54:49-00:00

Communications, IEEE Transactions on, Vol. 44, No. 6. (1996), pp. 668-674.

This paper considers discrete time analyses of digital delay lock loops (DDLL), and presents the results of an investigation concerning the performance degradation due to Doppler. The performance measures evaluated include the steady-state timing error probability density function (PDF) and the mean time to lose lock. The linear approximations are also provided and compared to the numerical results and simulations. The delay lock loop is a well-known technique to track the pseudo-noise (PN) codes for spread spectrum systems. Under a severe Doppler environment, such as in the low Earth orbit (LEO) satellite communication, it will be difficult to track the PN code for the first-order loop. Since the digital systems are more compact, lower cost, and more stable than their analog counterparts, we focus our attention on the digital first and second order code tracking loops that suffer from severe Doppler

Performance analysis of digital delay lock loops in the presence of Doppler shift

Szu-Lin Su — 2008-05-21T12:54:47-00:00

Communications, 1995. ICC '95 Seattle, 'Gateway to Globalization', 1995 IEEE International Conference on, Vol. 3 (1995), pp. 1896-1900 vol.3.

The delay lock loop is a well-developed technique to track the pseudo-noise codes for spread-spectrum systems. In previous papers the first-order loop was analyzed in the absence of Doppler shift. However, under severe Doppler environment, such as low-earth-orbit (LEO) satellite communication, the tracking of PN code will be difficult for the first-order loop. This paper considers discrete time analyses of first- and second-order digital delay lock loops (DDLL), and presents the results of an investigation concerning the performance degradation due to Doppler. The performance measures evaluated include the steady-state timing error probability density function (pdf) and the mean time to lose lock. The measures are characterized in terms of the Doppler shift and the loop signal-to-noise ratio. Moreover, approximate expressions for the steady-state timing error probability density and the mean time to lose lock are also presented for the first- and second-order digital delay lock loops. The analyses are confirmed by numerical results and simulation

Analysis and Optimization of Correlative Code-Tracking Loops in Spread-Spectrum Systems

A Polydoros — 2008-05-21T12:54:39-00:00

Communications, IEEE Transactions on [legacy, pre - 1988], Vol. 33, No. 1. (1985), pp. 30-43.

The purpose of this paper is to apply the renewal theory approach for analyzing aperiodic finite<tex>S</tex>-curve code-tracking loops developed by Meyr [9] to the case of a noncoherent, arbitrary offset, early-late, delay-locked loop ("noncoherent δ-DLL"). The exact (renewal) approach is compared to the approximate (periodic-extension) approach of using the periodic<tex>S</tex>-curve or phase-locked loop theory, as well as to the linear theory developed herein for the aforementioned codetracking loop. Finally, loop optimization with respect to the offset δ is carried out according to certain performance criteria. The results indicate that, for low SNR, the exact and approximate theories could deviate significantly while, for high SNR, all three theories yield identical performance, as expected. Furthermore, it is shown that the optimal δ for both low and high SNR could differ from the commonly accepted choice<tex>delta = 1/2</tex>.

Performance of digital code tracking loops for direct-sequence spread-spectrum signals in mobile radio channels

Szu-Lin Su — 2008-05-21T12:54:37-00:00

Communications, IEEE Transactions on, Vol. 45, No. 5. (1997), pp. 596-604.

The performance of first- and second-order non-coherent digital delay lock loops (DDLL) for direct-sequence spread-spectrum (DS-SS) signals is investigated in the mobile radio environment. The mobile radio channel is first characterized by Rayleigh fading and Doppler shift. A closed-form expression for the timing error transition probability density function of the Chapman-Kolmogorov (C-K) equation is proposed. The probability density function of the steady-state timing error for the first- and second-order DDLL is obtained by solving the C-K equation numerically, and the results are confirmed by computer simulations. Furthermore, the mean time to lose lock (MTLL) of the first-order loop is evaluated, and some numerical results and simulation results are reported. Finally, the steady-state timing error and MTLL of the first-order loop for DS-SS signals in the log-normal fading environment are also presented, and the results are compared with those of Rayleigh and AWGN channels

Performance Assessment of the TurboDLL for Satellite Navigation Receivers

Fabio Dovis — 2008-05-16T14:53:41-00:00

Satellite Communications and Navigation Systems (2008), pp. 273-282.

In this paper a detailed evaluation of the performance of the architecture named “Turbo Delay Lock Loop” (TurboDLL) is presented. Such an architecture has been introduced by the authors in [1], as an innovative solution for improving the performance of satellite navigation receivers in multipath affected scenarios. The relevant innovation resides in the fact that the architecture aims at tracking each multipath component and, after a transient time, use them to wipe the multipath components off the input signal. The iterative procedure allows for a major improvement in the error induced in the code-based pseudorange measurement. The architecture uses a preliminary estimation of the propagation channel in terms of number of not negligible reflections, and of their relative amplitude. In this paper the robustness of the TurboDLL architecture with respect to imperfect channel estimation is demonstrated.

Performance Analysis and Parameter Optimization of DLL and MEDLL in Fading Multipath Environments for Next Generation Navigation Receivers

M Sanchez-Fernandez — 2008-05-10T00:01:43-00:00

Consumer Electronics, IEEE Transactions on, Vol. 53, No. 4. (2007), pp. 1302-1308.

In this paper the choice of DLL parameters is studied with special focus on multipath and Doppler sensitivity. The envisaged application is code tracking on navigation receivers and the multipath fading environments defined for next generation navigation systems are considered. Given the particular properties of these propagation environments, multipath estimating delay lock loop is shown to have the best performance within a particular signal to noise ratio range if some specific parameters such as the Predetection Integration Time and channel estimation time interval match the time-varying nature of the channel and the spacing in the early-late scheme is chosen accordingly to the multipath characteristics.

Evolution of Multipath Error Reduction with Signal Processing

Alexey Zhdanov — 2008-02-11T10:59:24-00:00

GPS Solutions, Vol. 5, No. 3. (20 January 2002), pp. 19-28.

The described method of code and carrier multipath error reduction is a refinement of the strobe method of pseudo random noise (PRN) signal processing. This method utilizes as a correlator reference code a strobe sequence containing pulses with a specially designed shape. The method demonstrated its efficiency for reduction of the tracking error in PRN-signal digital receivers. Since the strobe method degrades signal to noise ratio, i. e., degrades the noise tracking error, a narrowing of the tracking system bandwidth is normally used to compensate for this degradation. This, in turn, could cause large dynamics errors in the measurements. However, in the present article, the strobe sequence is optimized to provide the best trade-off between multipath and noise/dynamic errors; i. e., the multipath error is reduced without a large increase of noise/dynamic error. The newly found strobe sequences are cited in the article, along with methods for their mathematical synthesis. Finally, theoretical and experimental results for noise and multipath errors are given. © 2002 Wiley Periodicals, Inc.

GPS receiver architectures and measurements

MS Braasch — 2008-02-11T09:58:35-00:00

Proceedings of the IEEE, Vol. 87, No. 1. (1999), pp. 48-64.

Although originally developed for the military, the Global Positioning System (GPS) has proven invaluable for a multitude of civilian applications. Each application demands specific performance from the GPS receiver and the associated requirements often vary widely. This paper describes the architectures and functions of civilian GPS receivers and then focuses on performance considerations. The fundamental receiver measurements are described and the quality of these measurements are related to the aforementioned receiver architectures