Fractal capacitors

by: H Samavati, A Hajimiri, AR Shahani, GN Nasserbakht, TH Lee

Solid-State Circuits, IEEE Journal of, Vol. 33, No. 12. (1998), pp. 2035-2041.

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Abstract

A linear capacitor structure using fractal geometries is described. This capacitor exploits both lateral and vertical electric fields to increase the capacitance per unit area. Compared to standard parallel-plate capacitors, the parasitic bottom-plate capacitance is reduced. Unlike conventional metal-to-metal capacitors, the capacitance density increases with technology scaling. A classic fractal structure is implemented with 0.6-μm metal spacing, and a factor of 2.3 increase in the capacitance per unit area is observed. It is shown that capacitance boost factors in excess of ten may be possible as technology continues to scale. A computer-aided-design tool to automatically generate and analyze custom fractal layouts has been developed

@article{citeulike:2060666, abstract = {A linear capacitor structure using fractal geometries is described. This capacitor exploits both lateral and vertical electric fields to increase the capacitance per unit area. Compared to standard parallel-plate capacitors, the parasitic bottom-plate capacitance is reduced. Unlike conventional metal-to-metal capacitors, the capacitance density increases with technology scaling. A classic fractal structure is implemented with 0.6-\μm metal spacing, and a factor of 2.3 increase in the capacitance per unit area is observed. It is shown that capacitance boost factors in excess of ten may be possible as technology continues to scale. A computer-aided-design tool to automatically generate and analyze custom fractal layouts has been developed}, author = {Samavati, H. and Hajimiri, A. and Shahani, A. R. and Nasserbakht, G. N. and Lee, T. H. }, booktitle = {Solid-State Circuits, IEEE Journal of}, citeulike-article-id = {2060666}, journal = {Solid-State Circuits, IEEE Journal of}, keywords = {capacitor, fractal}, number = {12}, pages = {2035--2041}, posted-at = {2007-12-05 11:56:33}, priority = {2}, title = {Fractal capacitors}, url = {http://ieeexplore.ieee.org/xpls/abs\_all.jsp?arnumber=735545}, volume = {33}, year = {1998} }

RIS record

TY - JOUR ID - citeulike:2060666 L3 - citeulike-article-id:2060666 TI - Fractal capacitors T2 - Solid-State Circuits, IEEE Journal of JF - Solid-State Circuits, IEEE Journal of VL - 33 IS - 12 SP - 2035 EP - 2041 N2 - A linear capacitor structure using fractal geometries is described. This capacitor exploits both lateral and vertical electric fields to increase the capacitance per unit area. Compared to standard parallel-plate capacitors, the parasitic bottom-plate capacitance is reduced. Unlike conventional metal-to-metal capacitors, the capacitance density increases with technology scaling. A classic fractal structure is implemented with 0.6-μm metal spacing, and a factor of 2.3 increase in the capacitance per unit area is observed. It is shown that capacitance boost factors in excess of ten may be possible as technology continues to scale. A computer-aided-design tool to automatically generate and analyze custom fractal layouts has been developed KW - capacitor KW - fractal AU - Samavati, H AU - Hajimiri, A AU - Shahani, AR AU - Nasserbakht, GN AU - Lee, TH PY - 1998/// UR - http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=735545 ER -

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