Methodology for on-chip adaptive jitter minimization in phase-locked loops

by: M Mansuri, A Hadiashar, Chih-Kong K Yang

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on], Vol. 50, No. 11. (2003), pp. 870-878.

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Abstract

This paper describes a run-time adaptive method of minimizing jitter for a phase-locked loop (PLL). The design employs digital tuning that independently adjusts each loop parameter of the PLL. The loop is fabricated in 0.25 /spl mu/m CMOS and uses a 2.5 V supply. The proposed method measures the output jitter on-chip and adjusts the PLL loop parameters toward minimizing the jitter by a closed-loop control system. The experimental results verify the success of the proposed method in minimizing jitter to within 5 ps of the minimum peak-to-peak jitter.

@article{citeulike:2782005, abstract = {This paper describes a run-time adaptive method of minimizing jitter for a phase-locked loop (PLL). The design employs digital tuning that independently adjusts each loop parameter of the PLL. The loop is fabricated in 0.25 /spl mu/m CMOS and uses a 2.5 V supply. The proposed method measures the output jitter on-chip and adjusts the PLL loop parameters toward minimizing the jitter by a closed-loop control system. The experimental results verify the success of the proposed method in minimizing jitter to within 5 ps of the minimum peak-to-peak jitter.}, author = {Mansuri, M. and Hadiashar, A. and Yang, Chih-Kong K. }, booktitle = {Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on]}, citeulike-article-id = {2782005}, doi = {10.1109/TCSII.2003.819124}, journal = {Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on]}, keywords = {jitter, pll, time}, number = {11}, pages = {870--878}, posted-at = {2008-05-10 00:45:10}, priority = {2}, title = {Methodology for on-chip adaptive jitter minimization in phase-locked loops}, url = {http://dx.doi.org/10.1109/TCSII.2003.819124}, volume = {50}, year = {2003} }

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TY - JOUR ID - citeulike:2782005 TI - Methodology for on-chip adaptive jitter minimization in phase-locked loops T2 - Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on] JF - Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on] VL - 50 IS - 11 SP - 870 EP - 878 N2 - This paper describes a run-time adaptive method of minimizing jitter for a phase-locked loop (PLL). The design employs digital tuning that independently adjusts each loop parameter of the PLL. The loop is fabricated in 0.25 /spl mu/m CMOS and uses a 2.5 V supply. The proposed method measures the output jitter on-chip and adjusts the PLL loop parameters toward minimizing the jitter by a closed-loop control system. The experimental results verify the success of the proposed method in minimizing jitter to within 5 ps of the minimum peak-to-peak jitter. KW - jitter KW - pll KW - time AU - Mansuri, M AU - Hadiashar, A AU - Yang, Chih-Kong PY - 2003/// UR - http://dx.doi.org/10.1109/TCSII.2003.819124 ER -

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