| Registrer deg | Logg på | FAQ | [?] |
Mean Time to Lose Lock for a PLL with Loop Delay under Thermal and Phase Noise ConditionsCommunications, 2007. ICC '07. IEEE International Conference on (2007), pp. 2888-2893.
|
Reviews
[Write a review of this article]
There are no reviews of this article
Find related articles from these CiteULike users
Find related articles with these CiteULike tags
AbstractThe growing demand for reliable communications leads to the need for very large mean time to lose lock (MTLL) of PLL based synchronization subsystems. These large MTLLs, of the order of months, cannot be simulated or tested in a lab. In this work a systematic approach is given to computing the MTLL of a second order PLL with parasitic delay at low SNR and high phase noise. Computed and simulated results are shown to be in good agreement for values that can be simulated.
BibTeX record
RIS record