A low-noise phase-locked loop design by loop bandwidth optimization

by: Kyoohyun Lim, Chan-Hong Park, Dal-Soo Kim, Beomsup Kim

Solid-State Circuits, IEEE Journal of, Vol. 35, No. 6. (2000), pp. 807-815.

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Abstract

This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter from a given PLL circuit topology. An optimal loop-bandwidth design method, derived from a discrete-time PLL model, further improves the jitter characteristics of a PLL already somewhat enhanced by optimizing individual circuit components. The described method not only estimates the timing jitter of a PLL, but also finds the optimal bandwidth minimizing the overall PLL jitter. A prototype PLL fabricated in a 0.6-μm CMOS technology is tested. The measurement shows significant performance improvement by using the proposed method, The measured rms and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 3.1 and 22 ps, respectively

@article{citeulike:2782972, abstract = {This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter from a given PLL circuit topology. An optimal loop-bandwidth design method, derived from a discrete-time PLL model, further improves the jitter characteristics of a PLL already somewhat enhanced by optimizing individual circuit components. The described method not only estimates the timing jitter of a PLL, but also finds the optimal bandwidth minimizing the overall PLL jitter. A prototype PLL fabricated in a 0.6-\μm CMOS technology is tested. The measurement shows significant performance improvement by using the proposed method, The measured rms and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 3.1 and 22 ps, respectively}, author = {Lim, Kyoohyun and Park, Chan-Hong and Kim, Dal-Soo and Kim, Beomsup }, booktitle = {Solid-State Circuits, IEEE Journal of}, citeulike-article-id = {2782972}, doi = {10.1109/4.845184}, journal = {Solid-State Circuits, IEEE Journal of}, keywords = {bandwidth, design, low, noise, pll}, number = {6}, pages = {807--815}, posted-at = {2008-05-10 15:39:11}, priority = {2}, title = {A low-noise phase-locked loop design by loop bandwidth optimization}, url = {http://dx.doi.org/10.1109/4.845184}, volume = {35}, year = {2000} }

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TY - JOUR ID - citeulike:2782972 TI - A low-noise phase-locked loop design by loop bandwidth optimization T2 - Solid-State Circuits, IEEE Journal of JF - Solid-State Circuits, IEEE Journal of VL - 35 IS - 6 SP - 807 EP - 815 N2 - This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter from a given PLL circuit topology. An optimal loop-bandwidth design method, derived from a discrete-time PLL model, further improves the jitter characteristics of a PLL already somewhat enhanced by optimizing individual circuit components. The described method not only estimates the timing jitter of a PLL, but also finds the optimal bandwidth minimizing the overall PLL jitter. A prototype PLL fabricated in a 0.6-μm CMOS technology is tested. The measurement shows significant performance improvement by using the proposed method, The measured rms and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 3.1 and 22 ps, respectively KW - bandwidth KW - design KW - low KW - noise KW - pll AU - Lim, Kyoohyun AU - Park, Chan-Hong AU - Kim, Dal-Soo AU - Kim, Beomsup PY - 2000/// UR - http://dx.doi.org/10.1109/4.845184 ER -

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