A low-power digital matched filter for direct-sequence spread-spectrum signal acquisition

@article{citeulike:2802210, abstract = {This paper presents a low-power 128-tap dual-channel direct-sequence spread-spectrum (DSSS) digital matched-filter chip. Design techniques used to reduce the power consumption of the system include latch-based register file filter structure, a high-rate compression scheme, optimized compressor cells, and semicustom layout design. To further reduce the power consumption and the hardware requirement of the clock tree, a double-edge-triggered clocking scheme is adopted. The proposed chip is fabricated using a 0.8-\μm standard CMOS process. As the experimental results of the chip indicate, the matched filter can operate at 50 MHz and dissipates 184 mW at 5-V supply voltage. The supply voltage can be scaled down to 2 V for lower speed applications. As a consequence, the proposed design has low power consumption and can be used for code acquisition of DSSS signals in portable systems}, author = {Lieu, Ming-Luen and Chiueh, Tzi-Dar }, booktitle = {Solid-State Circuits, IEEE Journal of}, citeulike-article-id = {2802210}, doi = {10.1109/4.924856}, journal = {Solid-State Circuits, IEEE Journal of}, keywords = {acquisition, signal, spread-spectrum}, number = {6}, pages = {933--943}, posted-at = {2008-05-15 18:44:01}, priority = {2}, title = {A low-power digital matched filter for direct-sequence spread-spectrum signal acquisition}, url = {http://dx.doi.org/10.1109/4.924856}, volume = {36}, year = {2001} }

TY - JOUR ID - citeulike:2802210 L3 - citeulike-article-id:2802210 TI - A low-power digital matched filter for direct-sequence spread-spectrum signal acquisition T2 - Solid-State Circuits, IEEE Journal of JF - Solid-State Circuits, IEEE Journal of VL - 36 IS - 6 SP - 933 EP - 943 N2 - This paper presents a low-power 128-tap dual-channel direct-sequence spread-spectrum (DSSS) digital matched-filter chip. Design techniques used to reduce the power consumption of the system include latch-based register file filter structure, a high-rate compression scheme, optimized compressor cells, and semicustom layout design. To further reduce the power consumption and the hardware requirement of the clock tree, a double-edge-triggered clocking scheme is adopted. The proposed chip is fabricated using a 0.8-μm standard CMOS process. As the experimental results of the chip indicate, the matched filter can operate at 50 MHz and dissipates 184 mW at 5-V supply voltage. The supply voltage can be scaled down to 2 V for lower speed applications. As a consequence, the proposed design has low power consumption and can be used for code acquisition of DSSS signals in portable systems KW - acquisition KW - signal KW - spread-spectrum AU - Lieu, Ming-Luen AU - Chiueh, Tzi-Dar PY - 2001/// UR - http://dx.doi.org/10.1109/4.924856 ER -