Analysis of convolutional encoders and synthesis of rate-2/n Viterbi decoders

@article{citeulike:2805132, abstract = {In this correspondence, the problem of obtaining efficient hardware for Viterbi decoders for high-rate convolutional encoders is addressed. It is first shown that the graphs describing the interconnection of the add-compare-select units required may be classified in terms of structures of which there are only a small number for a given code constraint length. They correspond to the assignment of individual register lengths in the ensemble of shift registers in the feedforward encoder. The structures relate to the partitioning of the states such that common successors are grouped together and successive partitioning leads to a hierarchical, modular VLSI layout method. Example symbolic grid layouts are given for 16- and 64-state codes. It is noted that within a given structure, the parity check matrices map into local wiring patterns implying a method for implementing class-universal programmable or adaptive decoders}, author = {Summerfield, S. }, booktitle = {Information Theory, IEEE Transactions on}, citeulike-article-id = {2805132}, doi = {10.1109/18.508860}, journal = {Information Theory, IEEE Transactions on}, keywords = {code, convolutional, decoder, viterbi}, number = {4}, pages = {1280--1285}, posted-at = {2008-05-16 12:48:34}, priority = {2}, title = {Analysis of convolutional encoders and synthesis of rate-2/n Viterbi decoders}, url = {http://dx.doi.org/10.1109/18.508860}, volume = {42}, year = {1996} }

TY - JOUR ID - citeulike:2805132 L3 - citeulike-article-id:2805132 TI - Analysis of convolutional encoders and synthesis of rate-2/n Viterbi decoders T2 - Information Theory, IEEE Transactions on JF - Information Theory, IEEE Transactions on VL - 42 IS - 4 SP - 1280 EP - 1285 N2 - In this correspondence, the problem of obtaining efficient hardware for Viterbi decoders for high-rate convolutional encoders is addressed. It is first shown that the graphs describing the interconnection of the add-compare-select units required may be classified in terms of structures of which there are only a small number for a given code constraint length. They correspond to the assignment of individual register lengths in the ensemble of shift registers in the feedforward encoder. The structures relate to the partitioning of the states such that common successors are grouped together and successive partitioning leads to a hierarchical, modular VLSI layout method. Example symbolic grid layouts are given for 16- and 64-state codes. It is noted that within a given structure, the parity check matrices map into local wiring patterns implying a method for implementing class-universal programmable or adaptive decoders KW - code KW - convolutional KW - decoder KW - viterbi AU - Summerfield, S PY - 1996/// UR - http://dx.doi.org/10.1109/18.508860 ER -