A SiGe PA with dual dynamic bias control and memoryless digital predistortion for WCDMA handset applications

@inproceedings{05-Deng, abstract = {The paper demonstrates a two-stage 1.95 GHz WCDMA handset RFIC power amplifier (PA) implemented in 1.8 mm/sup 2/ in a 250 nm SiGe BiCMOS process. With an integrated dual dynamic bias control of the collector current and the collector voltage in the output stage, the average power efficiency of the two-stage PA is improved by over a factor of two. An off-chip memoryless digital predistortion is also adopted to improve the linearity of the power amplifier, satisfying the 3GPP WCDMA adjacent channel power ratio (ACPR) specifications with 26 dBm average channel output power and a peak power-added efficiency of 27\%.}, author = {Deng, Junxiong and Gudem, P. and Larson, L. E. and Kimball, D. and Asbeck, P. M. }, booktitle = {Radio Frequency integrated Circuits (RFIC) Symposium, 2005. Digest of Papers. 2005 IEEE}, citeulike-article-id = {2754924}, doi = {http://dx.doi.org/10.1109/RFIC.2005.1489774}, journal = {Radio Frequency integrated Circuits (RFIC) Symposium, 2005. Digest of Papers. 2005 IEEE}, keywords = {asbeck, dpd, handset, implementation, kimball, sige, wcdma}, pages = {247--250}, posted-at = {2008-05-05 03:47:12}, priority = {2}, title = {A SiGe PA with dual dynamic bias control and memoryless digital predistortion for WCDMA handset applications}, url = {http://dx.doi.org/10.1109/RFIC.2005.1489774}, year = {2005} }

TY - CONF ID - 05-Deng L3 - citeulike-article-id:2754924 TI - A SiGe PA with dual dynamic bias control and memoryless digital predistortion for WCDMA handset applications T2 - Radio Frequency integrated Circuits (RFIC) Symposium, 2005. Digest of Papers. 2005 IEEE JF - Radio Frequency integrated Circuits (RFIC) Symposium, 2005. Digest of Papers. 2005 IEEE SP - 247 EP - 250 N2 - The paper demonstrates a two-stage 1.95 GHz WCDMA handset RFIC power amplifier (PA) implemented in 1.8 mm/sup 2/ in a 250 nm SiGe BiCMOS process. With an integrated dual dynamic bias control of the collector current and the collector voltage in the output stage, the average power efficiency of the two-stage PA is improved by over a factor of two. An off-chip memoryless digital predistortion is also adopted to improve the linearity of the power amplifier, satisfying the 3GPP WCDMA adjacent channel power ratio (ACPR) specifications with 26 dBm average channel output power and a peak power-added efficiency of 27%. KW - asbeck KW - dpd KW - handset KW - implementation KW - kimball KW - sige KW - wcdma AU - Deng, Junxiong AU - Gudem, P AU - Larson, LE AU - Kimball, D AU - Asbeck, PM PY - 2005/// UR - http://dx.doi.org/10.1109/RFIC.2005.1489774 ER -