Low-complexity high-speed decoder design for quasi-cyclic LDPC codes

by: ZF Wang, ZQ Cui

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol. 15, No. 1. (2007), pp. 104-114.

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array, bibtex-import, check, codes, correction, density, error, field, fpga, gate, ldpc, low, parallel, parity, parity-check, processing, programmable, qc, quasi-cyclic

Abstract

This paper studies low-complexity high-speed decoder architectures for quasi-cyclic low density parity check (QC-LDPC) codes. Algorithmic transformation and architectural level optimization are incorporated to reduce the critical path. Enhanced partially parallel decoding architectures are proposed to linearly increase the throughput of conventional partially parallel decoders through introducing a small percentage of extra hardware. Based on the proposed architectures, a (8176,7154) Euclidian geometry-based QC-LDPC code decoder is implemented on Xilinx field programmable gate array (FPGA) Virtex-II 6000, where an efficient nonuniform quantization scheme is employed to reduce the size of memories storing soft messages. FPGA implementation results show that the proposed decoder can achieve a maximum (source data) decoding throughput of 172 Mb/s at 15 iterations.

@article{RefWorks:168, abstract = {This paper studies low-complexity high-speed decoder architectures for quasi-cyclic low density parity check (QC-LDPC) codes. Algorithmic transformation and architectural level optimization are incorporated to reduce the critical path. Enhanced partially parallel decoding architectures are proposed to linearly increase the throughput of conventional partially parallel decoders through introducing a small percentage of extra hardware. Based on the proposed architectures, a (8176,7154) Euclidian geometry-based QC-LDPC code decoder is implemented on Xilinx field programmable gate array (FPGA) Virtex-II 6000, where an efficient nonuniform quantization scheme is employed to reduce the size of memories storing soft messages. FPGA implementation results show that the proposed decoder can achieve a maximum (source data) decoding throughput of 172 Mb/s at 15 iterations.}, author = {Wang, Z. F. and Cui, Z. Q. }, citeulike-article-id = {1477073}, journal = {IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS}, keywords = {array, bibtex-import, check, codes, correction, density, error, field, fpga, gate, ldpc, low, parallel, parity, parity-check, processing, programmable, qc, quasi-cyclic}, number = {1}, pages = {104--114}, posted-at = {2007-07-24 15:37:57}, priority = {5}, title = {Low-complexity high-speed decoder design for quasi-cyclic LDPC codes}, volume = {15}, year = {2007} }

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TY - JOUR ID - RefWorks:168 L3 - citeulike-article-id:1477073 TI - Low-complexity high-speed decoder design for quasi-cyclic LDPC codes JF - IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VL - 15 IS - 1 SP - 104 EP - 114 N2 - This paper studies low-complexity high-speed decoder architectures for quasi-cyclic low density parity check (QC-LDPC) codes. Algorithmic transformation and architectural level optimization are incorporated to reduce the critical path. Enhanced partially parallel decoding architectures are proposed to linearly increase the throughput of conventional partially parallel decoders through introducing a small percentage of extra hardware. Based on the proposed architectures, a (8176,7154) Euclidian geometry-based QC-LDPC code decoder is implemented on Xilinx field programmable gate array (FPGA) Virtex-II 6000, where an efficient nonuniform quantization scheme is employed to reduce the size of memories storing soft messages. FPGA implementation results show that the proposed decoder can achieve a maximum (source data) decoding throughput of 172 Mb/s at 15 iterations. KW - array KW - bibtex-import KW - check KW - codes KW - correction KW - density KW - error KW - field KW - fpga KW - gate KW - ldpc KW - low KW - parallel KW - parity KW - parity-check KW - processing KW - programmable KW - qc KW - quasi-cyclic AU - Wang, ZF AU - Cui, ZQ PY - 2007/// ER -

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