rdysydc's tags

013-micron 23-mm 3-bit 46-gbit-s 4-bit analog application-specific-integrated-circuits approximation approximation- approximation-theory architecture area-power-sensitive-high-speed-communication-systems array array-ldpc-codes asic-implementation behavior belief ber bibtex-import bounds bp capacity channel channels check code codecs- codes coding column-processing communication communications complexity convergence correcting correction cyclic-codes decision decoder decoding density design digital distribution effect efficient equalization equalizer error error-correction-codes error-floor-region fading fec feedback field field-programmable-gate-arrays floor forward-error fpga fpga-implementation gate ghost graphs high-throughput-ldpc-decoder information integrated-logic-circuits interference intersymbol isi iterative iterative-decoding joint-row-column-decoding-algorithm kerr layered-decoding ldpc ldpc-code ldpc-codes ldpc-decoders limit lines logic-design look-up low low-density low-density-parity-check-codes low-density-parity-check-decoder markov mathematical matrix-algebra memory memory-efficient-partially-parallel-decoder-architecture message-passing minimisation- min-sum min-sum-algorithm min-sum-data-reuse min-sum-objective-functions mmse models modulation ms multilevel multistage nonbinary nonlinearities optical optimized-nonuniform-quantization parallel parallel-architectures parallel-decoder parallel-processing parallel-vlsi-architecture parity parity-check parity-check-codes performance permutation-matrices polynomial processing programmable propagation pulses qc quantisation-signal quasi-cyclic quasi-cyclic-codes quasicyclic-ldpc-codes quasicyclic-low-density-parity-check-codes receivers reduced-hardware-complexity reduction routing-congestion row-processing scheduling shannon single-machine-scheduling speed state subscriber successive system tables theory thresholds throughput turbo turbo-like vlsi vlsi- weight with xilinx-xc4lx160-device

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