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A 1.3 V low-power 430 MHz front-end using a standard digital CMOS process [ISM wireless link]

by: T Melly, AS Porret, CC Enz, M Kayal
Custom Integrated Circuits Conference, 1998., Proceedings of the IEEE 1998 (1998), pp. 503-506.


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A low-power and low-voltage (LP/LV) RF front-end operating at 430 MHz and implemented in a standard 0.5 μm digital CMOS process is described. Specific LP/LV bias techniques and design tradeoffs are discussed and their application to the design of a fully integrated direct-conversion receiver is presented. The RF building blocks including a 200 μA LNA, two different 50 μA mixers and a ring-oscillator with differential I-Q outputs consuming 300 μA at 430 MHz, have been manufactured and their performances measured. Taking into account the severe power budget, a total double sideband (DSB) noise figure of 17 dB was achieved, together with a spurious free dynamic range of 55 dB at 60 kHz bandwidth, which is sufficient for the targeted application


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